1 概述

• 經(jīng)過 add beq jal jalr load & store 指令的測(cè)試，模擬器主要流程都已打通。
• ecall 是對(duì)流程和框架影響比較大的最后一部功能。

1.1 RISC-V 中的相關(guān)重要概念

• We use the term exception to refer to an unusual condition occurring at run time associated with an instruction in the current RISC-V hart.
• We use the term interrupt to refer to an external asynchronous event that may cause a RISC-V hart to experience an unexpected transfer of control.
• We use the term trap to refer to the transfer of control to a trap handler caused by either an exception or an interrupt.

2 測(cè)試 ecall 的程序

.section .text
.global _start

# Entry point of the program
_start:
    # Load the address of the ecall handler
    la t0, ecall_handler
    csrw mtvec, t0

    # Set up a value in a register for testing
    li a0, 52       # Load immediate value 42 into a0

    ecall

    li a0, 54
    # Infinite loop to halt the program
    j _start

ecall_handler:
    li t0, 52       # Expected value in a0 for our test
    beq a0, t0, ecall_ret

ecall_error:
    li a0, 1
    j ecall_error

ecall_ret:
    csrr t1, mepc
    addi t1, t1, 4
    csrw mepc, t1
    li a0, 53
    mret

3 實(shí)現(xiàn)的主要功能點(diǎn)

• 只實(shí)現(xiàn)當(dāng)前用到的 CSR,以及訪問 CSR 寄存器的指令
• 添加 Trap, 處理 trap 流程，及時(shí)調(diào)整架構(gòu)
• 添加 Privilege Mode

4 參考資料

• RISC-V Exception and Interrupt implementation
• 《RISC-V CPU 處理器設(shè)計(jì)（上）》第 13 章——不得不說的故事——中斷和異常
• RISC-V 異常處理流程介紹