StarRC Solution
StarRC 解決方案
Semiconductor process technology has been continually scaling down for the past four??decades and the trend continues.?
半導(dǎo)體工藝技術(shù)一直在縮小已經(jīng)持續(xù)了四十多年，這個趨勢仍在繼續(xù)。
Shrinking process geometries, combined with the use of new device structures like FinFETs and an increasing number of metal layers at each new process node, are introducing millions of new parasitic effects in designs.
幾何預(yù)縮工序，結(jié)合使用新的器件結(jié)構(gòu)，如FinFET和在每個新的工藝節(jié)點上增加金屬層的數(shù)量，在設(shè)計中引入了數(shù)百萬個新的寄生效應(yīng)。
In addition, soaring design sizes and complexities are increasing the sensitivity of circuits to parasitics due to the increasing impact on signal timing, noise and power.
此外，由于對信號定時、噪聲和功率的影響越來越大，飆升的設(shè)計尺寸和復(fù)雜性增加了電路對寄生電路的靈敏度。
To ensure a successful silicon design and meet tapeout schedules, IC designers need an advanced parasitic extraction solution that delivers signoff accuracy and increased designer productivity.
為了確保成功的硅設(shè)計和滿足磁帶輸出計劃（tapeout:原意是指“下線”，指的是集成電路（IC）或印刷電路板（PCB）設(shè)計的最后步驟，也就是送交制造 ），IC設(shè)計人員需要一種先進(jìn)的寄生提取解決方案，精度和提高設(shè)計人員的生產(chǎn)力。
?Furthermore, they need a solution that is versatile enough to manage the full design spectrum from custom digital, analog/mixed-signal (AMS) to full chip memory and SoC designs.
此外，他們需要一個足夠通用的解決方案來管理從自定義數(shù)字、模擬/混合信號(AMS)到全芯片存儲器和SOC設(shè)計的完整設(shè)計頻譜。
Synopsys’ StarRC is the proven high-accuracy and high-performance parasitic extraction solution for digital and custom IC implementation and signoff verification (Figure 1).
新思科技的StarRC軟件為數(shù)字和自定義IC實施和signoff驗證提供了高進(jìn)度高性能的寄生參數(shù)提取解決方案
?Trusted by hundreds of semiconductor companies and used in thousands of production designs, StarRC provides sub-femtofarad-accurate technology for design at advanced process technologies.?
在數(shù)百家半導(dǎo)體公司的信任下，在數(shù)千種生產(chǎn)設(shè)計中使用，StarRC為先進(jìn)工藝技術(shù)的設(shè)計提供了高精度的技術(shù)。
It achieves its high accuracy by performing detailed modeling of device and interconnect parasitic effects in nanometer process technologies.
在納米工藝技術(shù)中，通過對器件的詳細(xì)建模和互連寄生效應(yīng)，實現(xiàn)了其高精度。
?The advanced modeling and accuracy is complemented with the embedded Rapid3D field solver technology for circuits that require even higher accuracy.
先進(jìn)的建模和精度與嵌入式快速三維場求解器技術(shù)相補充，用于需要更高精度的電路。
StarRC delivers industry-leading performance and capacity for users’ gate-level and transistor-level extraction needs.
StarRC提供行業(yè)領(lǐng)先的性能和容量，為用戶的門級和晶體管級提取需求。
StarRC’s multi-core distributed processing technology delivers excellent scalability for efficient utilization of available hardware,and its simultaneous multi-corner extraction (SMC) feature allows the increasing number of extraction corners required for analysis to be processed within a single run with significantly reduced runtime and disk usage.
StarRC的多核分布式處理技術(shù)為有效利用可用硬件提供了極好的可伸縮性，其同時多角提取(SMC)特性允許在一次運行中處理分析所需的提取角的數(shù)量增加，大大減少了運行時和磁盤的使用。
?Its seamless integration with Synopsys’ place-and-route IC Compiler? and IC Compiler II physical implementation, gold standard PrimeTime? static timing analysis (STA) signoff, Galaxy Custom Designer? mixed-signal implementation, IC Validator physical verification, CustomSim? circuit simulation and other third-party implementation and signoff tools enables users to significantly accelerate their design implementation and verification.
StarRC完美整合了。。。。。。.軟件使用戶能夠顯著加快其設(shè)計實現(xiàn)和驗證。
Benefits
優(yōu)勢
1.Foundry gold standard for extraction accuracy with broadest qualification and adoption
黃金標(biāo)準(zhǔn)的提取精度與最廣泛的資格和采用
2.Leader in advanced modeling, including FinFET and color-aware multi-patterning at 10nm/7nm and beyond.
高級建模的領(lǐng)先者，包括FinFET和顏色感知的多圖案在10nm/7nm和更高。
3.High performance and capacity for gate and transistor-level extraction, enabled by multi-core distributed processing and simultaneous multi-corner extraction
高性能和容量的門和晶體管級提取，啟用多核分布式處理和同時多角提取
4.Tightly integrated with industry leading IC Compiler II and PrimeTime solutions for faster full-flow ECO turn-around time
緊密結(jié)合行業(yè)領(lǐng)先的IC編譯器II和Prime時間解決方案，以更快的全流ECO周轉(zhuǎn)時間
5.Unified Rapid3D fast field solver for critical net, IP, and custom circuit extraction
統(tǒng)一臨界網(wǎng)、IP和自定義電路提取的統(tǒng)一Rapid3D快速場求解器
6.Advanced netlist reduction features for faster simulation turn-around time
先進(jìn)的Netlist減少功能，以更快的模擬周轉(zhuǎn)時間
7.Inductance extraction for high frequency digital RLC clock net analysis
高頻數(shù)字RLC時鐘網(wǎng)分析的電感提取
8.3D-IC extraction solution for interposer and stacked die technologies
3D-IC提取解決方案的干涉和堆疊模具技術(shù)
9. Integration with IC Validator physical verification, CustomSim circuit simulation, Galaxy Custom Designer and other third party implementation and custom design solutions for increased designer productivity
集成IC驗證器物理驗證、自定義SIM電路仿真、Galaxy自定義設(shè)計器等第三方實現(xiàn)和自定義設(shè)計解決方案，提高設(shè)計人員的生產(chǎn)力
