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For the following Karnaugh map, give the circuit implementation using one 4-to-1 multiplexer and as many 2-to-1 multiplexers as required, but using as few as possible. You are not allowed to use any other logic gate and you must use a and b as the multiplexer selector inputs, as shown on the 4-to-1 multiplexer below.
題目.png這里需要清楚對(duì)mux_in[0],mux_in[1],mux_in[3],mux_in[3]分別采用c,d的表述形式，就是你要清楚知道m(xù)ux_in[0]時(shí)是cd分別表示01，11，10時(shí)才會(huì)得到的結(jié)果。也就是當(dāng)c+d = 1時(shí)才會(huì)得到mux_in[0]= 1的表達(dá)。也就是意味著僅僅c,d都為0時(shí)，結(jié)果才會(huì)為0.
- HDLBits 這一部分的題目沒有什么好說的，就是直接按照真值表去畫卡諾圖然后化簡(jiǎn)寫出邏輯表達(dá)式就好。
- 卡諾圖化簡(jiǎn)
- SOP form 即與或式，對(duì)應(yīng)于卡諾圖就是圈1即可
- POS form 即或與式, 對(duì)應(yīng)于卡諾圖就是圈0后，整體取反
