本文目的
- secure world以及non secure world在CPU硬件中如何體現(xiàn)，如何切換
- Exception Level在CPU硬件中如何體現(xiàn)，怎么切換
CPU Exception Level
PSTATE.EL
EL Current Exception level, see Exception levels on page D1-2134. On a reset to AArch64 state, this field holds the encoding for the highest implemented Exception level.
Note:
The ARM architecture requires that a PE resets into the highest implemented Exception level.
訪問方法： mrs x0, CurrentEL
CurrentEL只讀，不可寫
切換方法
- 當(dāng)發(fā)生異常，可以提高或者保持相同的異常等級
- 當(dāng)從異常中返回，可以降低或保持相同的異常等級
CPU secure與non secure的表示
Secure狀態(tài)的切換在EL3中實(shí)現(xiàn)，EL3可以設(shè)置EL0和EL1的Secure狀態(tài)，通過設(shè)置SCR_EL3的NS位，在系統(tǒng)可以切換secure 和non secure。
// Set the Secure version of ICC_SRE_EL1
ISB
MRS x1, SCR_EL3
BIC w1, w1, #1 // Set NS bit (lower EL in Secure state)
MSR SCR_EL3, x1
外設(shè)以及內(nèi)存如何區(qū)分Secure State以及Exception Level？
- AMBA BUS中有專用的信號線進(jìn)行Access Permission的控制
AXI-Access-Permissions.png
AMBA AXI and ACE Protocol Specification AXI3, AXI4, and AXI4-Lite ACE and ACE-Lite
從上圖可知，AXI規(guī)定由AxPROT[0]指定傳輸是否是在特權(quán)等級，但這個(gè)限號只有一位，那么這里的特權(quán)等級到底指ELx呢？
image.png
AXI privilege information
Table 7.10. Cortex-A53 MPCore mode and ARPROT and AWPROT values
| Processor exception level | Type of access | Value of ARPROT[0] and AWPROT[0] |
|---|---|---|
| EL0, EL1, EL2, EL3 | Cacheable read access | Privileged access |
| EL0 | Device, or normal Non-cacheable read access | Unprivileged access |
| EL1, EL2, EL3 | Device, or normal Non-cacheable read access | Privileged access |
| EL0, EL1, EL2, EL3 | Cacheable write access | Privileged access |
| EL0 | Device, nGnRnE, nGnRE, and nGRE write | Unprivileged access |
| EL1, EL2, EL3 | Device, nGnRnE, nGnRE, and nGRE write | Privileged access |
| EL0 | Normal Non-cacheable or Device GRE write, except for STREX, STREXB, STREXH, STREXD, STXR, STXRB, STXRH, STXP, STLXR, STLXRB, STLXRH and STLXP to shareable memory | Privileged access |
| EL0 | Normal Non-cacheable write for STREX, STREXB, STREXH, STREXD, STXR STXRB, STXRH, STXP, STLXR, STLXRB, STLXRH and STLXP to shareable memory | Unprivileged access |
| EL1, EL2, EL3 | Normal Non-cacheable write | Privileged access |
| EL0, EL1, EL2, EL3 | TLB page walk | Privileged access |
目前看來，沒有直接的辦法，根據(jù)CPU的異常等級，來設(shè)置外設(shè)的訪問權(quán)限。只能通過MMU來設(shè)置權(quán)限
- 外設(shè)以及內(nèi)存DDR，SRAM等需要通過SOC內(nèi)專門的控制器來實(shí)現(xiàn)secure以及non-secure的劃分，切換，詳細(xì)見下面文章
TZPC(TrustZone Protection Controller)
Refs：
Changing Exception Level and Security State with an Armv8-A Fixed Virtual Platform
