This 8-bit wide 2-to-1 multiplexer doesn't work. Fix the bug(s).

module top_module (
    input sel,
    input [7:0] a,
    input [7:0] b,
    output[7:0] out  );

    //assign out = (~sel & a) | (sel & b);
    assign out = (sel==1)? a : b;

endmodule
-------------------官網(wǎng)答案----------------------------------------
module top_module (
    input sel,
    input [7:0] a,
    input [7:0] b,
    output reg [7:0] out
);

    // 1. A mux coded as (~sel & a) | (sel & b) does not work for vectors.
    // This is because these are bitwise operators, and sel is only a 1 bit wide quantity,
    // which leaves the upper bits of a and b zeroed. It is possible to code it using
    // the replication operator, but this is somewhat difficult to read:
    //   ( {8{~sel}} & a ) | ( {8{sel}} & b )
    
    // 2. The simulation waveform shows that when sel = 1, a should be selected. This
    // is flipped in the suggested code.

    assign out = sel ? a : b;
    
endmodule

This 4-to-1 multiplexer doesn't work. Fix the bug(s).

You are provided with a bug-free 2-to-1 multiplexer:

module mux2 (
    input sel,
    input [7:0] a,
    input [7:0] b,
    output [7:0] out
);

被給的待改代碼如下：

module top_module (
    input [1:0] sel,
    input [7:0] a,
    input [7:0] b,
    input [7:0] c,
    input [7:0] d,
    output [7:0] out  ); //

    wire mux0, mux1;
    mux2 mux0 ( sel[0],    a,    b, mux0 );
    mux2 mux1 ( sel[1],    c,    d, mux1 );
    mux2 mux2 ( sel[1], mux0, mux1,  out );
-----------------------------------更改情況-----------------
      //wire mux0, mux1;
    reg[7:0] mux0;
    reg[7:0] mux1;
    mux2 mux_0 ( sel[0],    a,    b, mux0 );
    mux2 mux_1 ( sel[0],    c,    d, mux1 );
    mux2 mux_2 ( sel[1], mux0, mux1,  out );
endmodule

• Bugs addsubz
  The following adder-subtractor with zero flag doesn't work. Fix the bug(s).

// synthesis verilog_input_version verilog_2001
module top_module ( 
    input do_sub,
    input [7:0] a,
    input [7:0] b,
    output reg [7:0] out,
    output reg result_is_zero
);//

    always @(*) begin
        case (do_sub)
          0: out = a+b;
          1: out = a-b;
        endcase

        if (~out)
            result_is_zero = 1;
    end

endmodule
----------------------------------------------------------------------------------------------
// synthesis verilog_input_version verilog_2001
module top_module ( 
    input do_sub,
    input [7:0] a,
    input [7:0] b,
    output reg [7:0] out,
    output reg result_is_zero
);//

    always @(*) begin
        case (do_sub)
          0: out = a+b;
          1: out = a-b;
        endcase

        if (out==0)
            result_is_zero = 1'd1;
        else
            result_is_zero = 1'd0;
    end

endmodule

• Bugs case
  This combinational circuit is supposed to recognize 8-bit keyboard scancodes for keys 0 through 9. It should indicate whether one of the 10 cases were recognized (valid), and if so, which key was detected. Fix the bug(s).

module top_module (
    input [7:0] code,
    output reg [3:0] out,
    output reg valid=1 );//

     always @(*)
        case (code)
            8'h45: out = 0;
            8'h16: out = 1;
            8'h1e: out = 2;
            8'd26: out = 3;
            8'h25: out = 4;
            8'h2e: out = 5;
            8'h36: out = 6;
            8'h3d: out = 7;
            8'h3e: out = 8;
            6'h46: out = 9;
            default: valid = 0;
        endcase

endmodule
----------------------------------參考答案-----------------------------------------
module top_module (
    input [7:0] code,
    output reg [3:0] out,
    output reg valid
);

    // A combinational always block.
    always @(*) begin
        out = 0;        // To avoid latches, give the outputs a default assignment
        valid = 1;      //   then override them in the case statement. This is less
                        //   code than assigning a value to every variable for every case.
        case (code)
            8'h45: out = 0;
            8'h16: out = 1;
            8'h1e: out = 2;
            8'h26: out = 3;     // 8'd26 is 8'h1a
            8'h25: out = 4;
            8'h2e: out = 5;
            8'h36: out = 6;
            8'h3d: out = 7;
            8'h3e: out = 8;
            8'h46: out = 9;
            default: valid = 0;
        endcase
    end
    
endmodule

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