interface接口模塊代碼

`ifndef ROUTER_INTERFACE_SV  // 防止代碼沖突
`define ROUTER_INTERFACE_SV

interface   router_interface(input clock);
  logic reset_n;
  logic [15:0] din;
  logic [15:0] frame_n; 
  logic [15:0] valid_n;
  logic [15:0] dout;
  logic [15:0] valido_n;
  logic [15:0] busy_n; 
  logic [15:0] frameo_n;


  clocking cbv @(posedge clk);
    output din,
    output frame_n, 
    output valid_n;
    input dout,
    input valido_n,
    input busy_n, 
    input frameo_n;
  endclocking :cb

  modport TB(clocking cb , output reser_n);



endinterface:router_interface


`endif // ROUTER_INTERFA

interface_reset_test代碼

`ifndef INTERFACE_RESERT_TEST
`define INTERFACE_RESET_TEST
program interface_reset_test(router_inferface.TB router_inf_tb);

  task reset();
    $display("interface_reset_test,reset enter.....")
    router_inf_tb.reset_n <= 1'b0;
    router_inf_tb.din  <= 'h0;
    router_inf_tb.frame_n <= 'h1;
    router_inf_tb.valido_n <= 'h1;

  
  endtask:reset



    inital begin


    end

endprogram:interface_reset_test
`endif //  INTERFACE_RESERT_TEST

tb_top 代碼：

`ifndef TB_TOP_SV
`define TB_TOP_SV

`include "tb_include.sv"
module tb_top;
  bit clk;
  // instance interface
  router_inferace u_router_interface(.clock());
  // instance dut
  router   u_router(
    .reset_n  (u_router_interface.reset_n), 
    .clock    (clk), 
    .frame_n  (u_router_interface.frame_n), 
    .valid_n  (u_router_interface.valid_n), 
    .din      (u_router_interface.din), 
    .dout     (u_router_interface.dout), 
    .busy_n   (u_router_interface.busy_n), 
    .valido_n (u_router_interface.valido_n), 
    .frameo_n (u_router_interface.frameo_n) 
  );


  // instance tc
  interface_reset_test u_interface_reset_test(u_router_interface);

  // clk 4ns
  initial begin
    clk = 0;
    forever #2  clk = ~clk;
  end



endmodule:tb_top



`enif TB_TOP_SV